Asynchronous Logic Design Principles in Asylog

1. Handshake Circuit Fundamentals

Asylog is built on the concept of handshake circuits, which are asynchronous circuits that communicate through handshake protocols rather than using a global clock. The key principles include:

Handshake Protocols

The project uses two main types of handshake channels:

1. Sync Channel (Control): A simple request-acknowledge protocol
   

   Master --req--> Slave
   Master <--ack-- Slave

2. Dual-Rail Data Channel (dlogic): Uses dual-rail encoding for data transfer
   • Push Channel: Data flows from master to slave
   • Pull Channel: Data flows from slave to master
   • Uses separate wires for positive (hidata) and negative (lodata) rails

Dual-Rail Encoding

Data is represented using dual-rail encoding, where each bit uses two physical wires:

• hidata: Represents the positive rail (logical '1')
• lodata: Represents the negative rail (logical '0')
• Valid data has exactly one of these wires active per bit
• When both are inactive, it represents a "spacer" or null value

This encoding provides:

• Delay-insensitivity (the circuit works regardless of wire delays)
• Self-timing (completion can be detected by observing the data rails)
• Robustness against hazards and glitches

2. Basic Building Blocks

The library contains several fundamental components:

Latches and Storage Elements

1. SELatch (Set-Enable Latch): A basic storage element controlled by set and enable signals
2. SRALatch (Set-Reset-Ack Latch): Used for storing data bits in variables
   • Stores a bit value and generates an acknowledgment when data is valid
3. SElem (S-Element): A control component that sequences operations
   • Implements a fundamental sequencing behavior for handshake circuits

Control Components

1. Sequence: Implements sequential execution of operations
   • Activates outputs one after another in sequence
2. Concur: Implements parallel execution of operations
   • Activates all outputs simultaneously
3. Loop: Generates repeated activations
   • Used for implementing loops and repetitive behaviors
4. While: Conditional repetition based on a guard condition
   • Continues executing as long as the guard condition is true
5. Bar: Implements guarded commands (selection between alternatives)
   • Routes control based on guard conditions

Data Components

1. Fetch: Transfers data from an input channel to an output channel
   • Synchronizes data transfer with control signals
2. Variable: Stores data values and provides read access
   • Implements storage with multiple read ports
3. BinaryFunc: Implements binary operations (like subtraction, comparison)
   • Performs operations on two input values

3. Compilation Process

The Asylog compiler translates high-level asynchronous descriptions into networks of handshake components:

1. Source Language: Asylog resembles SystemVerilog but with asynchronous semantics
   

   while select
   x > y:
       x = x - y;
   y > x:
       y = y - x;
   endselect

2. Target Implementation: SystemVerilog netlist of handshake components
   • The GCD example shows how the compiler transforms the high-level description into a network of While, Bar, BinaryFunc, and other components


3. Compilation Patterns:
   • always @(activate) blocks are translated into handshake control structures
   • Sequential statements become Sequence components
   • Parallel statements (fork-join) become Concur components
   • Loops become Loop or While components
   • Conditional statements become Bar components

4. Implementation Technologies

The project supports multiple implementation technologies:

1. Generic: Technology-independent implementations for simulation
   • Uses simple delay models for timing
2. Xilinx FPGA: Specialized implementations for Xilinx FPGAs
   • Uses LUTs and other FPGA primitives
3. Altera FPGA: Specialized implementations for Altera FPGAs

Each technology provides its own implementation of the basic components, optimized for the target platform.

5. Key Advantages of This Approach

1. Modularity: The design is built from reusable handshake components
2. Delay-Insensitivity: Circuits work correctly regardless of gate and wire delays
3. No Global Clock: Eliminates clock distribution and timing closure issues
4. Power Efficiency: Components are only active when processing data
5. Technology Independence: The same high-level design can target different technologies

6. Verification and Testing

The project includes extensive testing infrastructure:

• Unit tests for individual components
• Integration tests for complete designs
• Simulation support for various simulators (VCS, Xsim)
• FPGA implementation examples